The invention relates to a monolithically integrated semiconductor memory with a matrix of identical storage cells arranged in rows and columns, in the form of coordinated MOS-field-effect transistors and storage capacitors represented, for example, by MOS capacitors, wherein, also, a comparator and a comparison cell is represented by a storage cell of the aforementioned type, associated with each matrix column.
Memory circuits of this kind are described, for example, in "IEEE Journal of Solid-State Circuits" Vol. SC-7 (October, 1972), Pages 336-340.
In the conventional organization of such dynamically operated write-read memories, bit lines extending parallel to the rows and connected to the storage cells provided in the associated matrix column are provided for each column of the memory matrix, and are connected to the one input of a comparator formed as a bistable flip-flop. The comparison cell is then connected to the second signal input of the comparator.
Both the storage cells as well as the comparison cells are formed as so-called single-transistor memory cells. They are made up accordingly of transfer transistors (usually of the enhancement type), wherein the source or drain, are connected to the corresponding bit line, and the gate thereof is connected to a word line which is associated with the corresponding memory cell (and extends in parallel rows). The drain and the source, respectively, of the transfer or switching transistor is connected to one pole of a storage capacitor which is formed in particular of an MOS capacity, the second pole of which is connected to the reference potential of the circuit. A dummy line is provided for the comparison cell and corresponds to the word lines. It can be addressed simultaneously with the latter, while the source and the drain, respectively, of the transfer transistor thereof is connected to the other information-carrying terminal of the comparator. Otherwise, the circuit of the comparison or dummy cell is similar to that of the single-transistor storage cell.
In the interest of reducing the effect of the bit line capacity on the storage behavior and the operating speed of the matrix memory, the bit line of the individual matrix columns as well as the number of the single-transistor storage cells assigned to the corresponding matrix column will frequently be divided into two halves, wherein one of the halves will be associated with the one end and the other of the halves with the other of the hereinaforementioned signal inputs of the comparator. Each of the two bit line halves is provided with a corresponding comparison cell in the aforedescribed manner, which are then addressed via the gates thereof if an address of a single-transistor storage cell associated with the other bit line half is present.